In the field of telecommunications and data processing there are applications in which it is necessary to synchronize a first sequence of signals with a second such sequence. For example, it may be required to bring a locally generated signal sequence into alignment with a received signal sequence both in frequency and phase. To achieve this alignment the locally generated signal sequence needs to be continually locked to the phase of the received signal sequence. For this purpose circuit assemblies, termed phase aligners are put to use. An example of one such phase synchronizer reads from IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, November 1997 in “A Semidigital Dual Delay-Locked Loop”. This known phase synchronizer is in principle a circuit assembly for generating an output phase signal with an optionally variable phase shift relative to a reference phase, it including an oscillator outputting phase signals at n outputs each of which is shifted in phase by φ=360°/n from one output to the next and is correspondingly staggered in time relative to each other by Δt, a first multiplexer, the inputs of which are connected to the even-number outputs of the oscillator and which passes on to its output a phase signal output by an output x of the oscillator as a function of a phase selection signal determined by the phase output signal to be generated, a second multiplexer the inputs of which are connected to the odd-number outputs of the oscillator and which passes on to its output a phase signal output by an output x+1 of the oscillator as a function of a phase selection signal determined by the phase output signal to be generated, a phase interpolator receiving the phase signals output by the multiplexers and controlling with these the periodic opening and closing of phase switches in the time spacing of Δt, the phase interpolator containing a charging circuit in which a charging voltage of a capacitor is varied by switching current sources assigned to the phase switches on or off in accordance with the closing or opening of the phase switches, whereby a number of current sources is provided corresponding to the number of interphase shift values to be generated between the phase shifts of the phase signals determined by the phase select signal, to each of which at least two phase switches are assigned, of which the one in each case is controlled by the phase signal output by the first multiplexer and the other by the phase signal output by the second multiplexer, a first separating switch being inserted in the connection between each of the phase switches and the assigned current source.
This circuit assembly makes it possible by periodic opening and closing of the phase switches to generate output phase signals, the phasing of which continually varies relative to the reference phase so that the object of phase synchronization is achievable by another signal. Actual practice has shown, however, that on opening and closing the phase switches and in thereby varying the phase as wanted from one value to the next no smooth transition is attained, instead phase fluctuations, also termed jitter, materializing. These phase fluctuations are undesirable and need to be eliminated as best possible to achieve a quasi-continuous phase shift.